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NXP Semiconductors
PCA9634
8-bit Fm+ I 2 C-bus LED driver
7.3.4 GRPPWM: Group duty cycle control
Table 8. GRPPWM - Group duty cycle control register (address 0Ah) bit description
Legend: * default value.
Address
0Ah
Register
GRPPWM
Bit
7:0
Symbol
GDC[7:0]
Access
R/W
Value
1111 1111
Description
GRPPWM register
When DMBLNK bit (MODE2 register) is programmed with 0, a 190 Hz ?xed frequency
signal is superimposed with the 97 kHz individual brightness control signal. GRPPWM is
then used as a global brightness control allowing the LED outputs to be dimmed with the
same value. The value in GRPFREQ is then a ‘Don’t care’.
General brightness for the 8 outputs is controlled through 256 linear steps from 00h
(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 and LEDOUT1
registers).
When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers
de?ne a global blinking pattern, where GRPFREQ contains the blinking period (from
24 Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
GDC [ 7 : 0 ]
duty cycle = ---------------------------
256
7.3.5 GRPFREQ: Group frequency
Table 9. GRPFREQ - Group Frequency register (address 0Bh) bit description
Legend: * default value.
(2)
Address
0Bh
Register
GRPFREQ
Bit
7:0
Symbol
GFRQ[7:0]
Access
R/W
Value
0000 0000*
Description
GRPFREQ register
GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2
register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 and LEDOUT1
registers).
Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz)
to FFh (10.73 s).
global blinking period = ---------------------------------------- ( in sec onds )
PCA9634_6
GFRQ [ 7 : 0 ] + 1
24
(3)
? NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 12 September 2008
13 of 38
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